Contents
1.5 Delay-Insensitive Circuits
2.2 Structural Modeling in VHDL
3.8 Syntax-Directed Translation
4.2 Asynchronous Finite State Machines
4.2.1 Finite State Machines and Flow Tables
4.2.2 Burst-Mode State Machines
4.2.3 Extended Burst-Mode State Machines
4.3.2 Signal Transition Graphs
4.4 Timed Event/Level Structures
5.1.1 Matrix Reduction Techniques
5.2.1 Finding the Compatible Pairs
5.2.2 Finding the Maximal Compatibles
5.2.3 Finding the Prime Compatibles
Get Asynchronous Circuit Design now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.