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Asynchronous Circuit Design

Book Description

With asynchronous circuit design becoming a powerful tool in the development of new digital systems, circuit designers are expected to have asynchronous design skills and be able to leverage them to reduce power consumption and increase system speed. This book walks readers through all of the different methodologies of asynchronous circuit design, emphasizing practical techniques and real-world applications instead of theoretical simulation. The only guide of its kind, it also features an ftp site complete with support materials.

Market: Electrical Engineers, Computer Scientists, Device Designers, and Developers in industry.

An Instructor Support FTP site is available from the Wiley editorial department.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Dedication
  5. Contents
  6. Preface
  7. Acknowledgments
  8. Chapter 1: Introduction
    1. 1.1 PROBLEM SPECIFICATION
    2. 1.2 COMMUNICATION CHANNELS
    3. 1.3 COMMUNICATION PROTOCOLS
    4. 1.4 GRAPHICAL REPRESENTATIONS
    5. 1.5 DELAY-INSENSITIVE CIRCUITS
    6. 1.6 HUFFMAN CIRCUITS
    7. 1.7 MULLER CIRCUITS
    8. 1.8 TIMED CIRCUITS
    9. 1.9 VERIFICATION
    10. 1.10 APPLICATIONS
    11. 1.11 LET'S GET STARTED
    12. 1.12 SOURCES
    13. Problems
  9. Chapter 2: Communication Channels
    1. 2.1 BASIC STRUCTURE
    2. 2.2 STRUCTURAL MODELING IN VHDL
    3. 2.3 CONTROL STRUCTURES
    4. 2.4 DEADLOCK
    5. 2.5 PROBE
    6. 2.6 PARALLEL COMMUNICATION
    7. 2.7 EXAMPLE: MINIMIPS
    8. 2.8 SOURCES
    9. Problems
  10. Chapter 3: Communication Protocols
    1. 3.1 BASIC STRUCTURE
    2. 3.2 ACTIVE AND PASSIVE PORTS
    3. 3.3 HANDSHAKING EXPANSION
    4. 3.4 RESHUFFLING
    5. 3.5 STATE VARIABLE INSERTION
    6. 3.6 DATA ENCODING
    7. 3.7 EXAMPLE: TWO WINE SHOPS
    8. 3.8 SYNTAX-DIRECTED TRANSLATION
    9. 3.9 SOURCES
    10. Problems
  11. Chapter 4: Graphical Representations
    1. 4.1 GRAPH BASICS
    2. 4.2 ASYNCHRONOUS FINITE STATE MACHINES
    3. 4.3 PETRI NETS
    4. 4.4 TIMED EVENT/LEVEL STRUCTURES
    5. 4.5 SOURCES
    6. Problems
  12. Chapter 5: Huffman Circuits
    1. 5.1 SOLVING COVERING PROBLEMS
    2. 5.2 STATE MINIMIZATION
    3. 5.3 STATE ASSIGNMENT
    4. 5.4 HAZARD-FREE TWO-LEVEL LOGIC SYNTHESIS
    5. 5.5 EXTENSIONS FOR MIC OPERATION
    6. 5.6 MULTILEVEL LOGIC SYNTHESIS
    7. 5.7 TECHNOLOGY MAPPING
    8. 5.8 GENERALIZED C-ELEMENT IMPLEMENTATION
    9. 5.9 SEQUENTIAL HAZARDS
    10. 5.10 SOURCES
    11. Problems
  13. Chapter 6: Muller Circuits
    1. 6.1 FORMAL DEFINITION OF SPEED INDEPENDENCE
    2. 6.2 COMPLETE STATE CODING
    3. 6.3 HAZARD-FREE LOGIC SYNTHESIS
    4. 6.4 HAZARD-FREE DECOMPOSITION
    5. 6.5 LIMITATIONS OF SPEED-INDEPENDENT DESIGN
    6. 6.6 SOURCES
    7. Problems
  14. Chapter 7: Timed Circuits
    1. 7.1 MODELING TIMING
    2. 7.2 REGIONS
    3. 7.3 DISCRETE TIME
    4. 7.4 ZONES
    5. 7.5 POSET TIMING
    6. 7.6 TIMED CIRCUITS
    7. 7.7 SOURCES
    8. Problems
  15. Chapter 8: Verification
    1. 8.1 PROTOCOL VERIFICATION
    2. 8.2 CIRCUIT VERIFICATION
    3. 8.3 SOURCES
    4. Problems
  16. Chapter 9: Applications
    1. 9.1 BRIEF HISTORY OF ASYNCHRONOUS CIRCUIT DESIGN
    2. 9.2 AN ASYNCHRONOUS INSTRUCTION-LENGTH DECODER
    3. 9.3 PERFORMANCE ANALYSIS
    4. 9.4 TESTING ASYNCHRONOUS CIRCUITS
    5. 9.5 THE SYNCHRONIZATION PROBLEM
    6. 9.6 THE FUTURE OF ASYNCHRONOUS CIRCUIT DESIGN
    7. 9.7 SOURCES
    8. Problems
  17. Appendix A: VHDL Packages
    1. A.1 NONDETERMINISM.VHD
    2. A.2 CHANNEL.VHD
    3. A.3 HANDSHAKE.VHD
  18. Appendix B: Sets and Relations
    1. B.1 BASIC SET THEORY
    2. B.2 RELATIONS
  19. References
  20. Index