Arithmetic and Logic in Computer Systems

List of Figures

1.1 Floating-Point Representation

1.2 Range of the Numbers

1.3 Precision of Floating-Point Numbers

1.4 Double Precision Floating-Point Representation

2.1 AOI Function

2.2 Decoder and Multiplexer

2.3 Single-Bit Half-Adder

2.4 Design of Full-Adder

2.5 Single-Bit Subtrator

2.6 Negation in One's Complement System

2.7 Negation in Two's Complement System

2.8 Subtraction through Addition

2.9 One-Bit Adder/Subtractor

2.10 Two's Complement Addition/Subtraction

2.11 One's Complement Addition/Subtraction

2.12 Block Diagram of Sign-Magnitude Addition/Subtraction

2.13 Sign-Magnitude Addition/Subtraction

3.1 Conditional-Sum Addition

3.2 Conditional-Sum Adder

3.3 Generation and Transmission of Carries

3.4 Construction of Carry-Completion Sensing Adder

3.5 Carry-Lookahead Adder

3.6 Block Carry-Lookahead Adder

3.7 Carry-Save Adder

3.8 Carry-Save Adder Tree

3.9 Two Types of Parallelization in Multi-Operand Addition

3.10 Bit-Partitioned Multiple Addition

3.11 Carry-Completion Sensing Adder

3.12 Carry-Save Adder

3.13 Bit-Partitional Adder

4.1 Hardware for Sequential Multiplication

4.2 Register Occupation

4.3 Unsigned Number Multiplication

4.4 Sign-Magnitude Number Multiplication

4.5 One's Complement Number Multiplication

4.6 Two's Complement Number Multiplication

4.7 Negative Multiplicand Times Positive Multiplier

4.8 Negative Multiplicand Times Negative Multiplier

4.9 Multiple Bit Scanning

4.10 String Property

4.11 Two-Bit Scan vs. Overlapped Three-Bit Scan

4.12 Example of Booth's ...