1.1. Resistor Voltage Divider and MOSFET DC Gate Voltage
Figure 1.1(a) shows a basic NMOS amplifier stage. This is the dc (or bias) portion of the circuit, which excludes the signal part. The terminals of the transistor are designed G (gate), D (drain) and S (source). The design calls for a dc voltage VG, with respect to the zero reference voltage, which is obtained by dividing the supply voltage VDD between bias resistors RG1 and RG2. Since the gate terminal has zero current, the voltage, VG, at the gate can be assessed with the resistor network separated from the circuit as in Fig. 1.1(b). The goal is to relate the node voltage VG to the values of RG1 and RG2 and VDD. The result is the basic resistor voltage-divider relation.
Figure 1.1. ...
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