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All-Digital Frequency Synthesizer in Deep-Submicron CMOS by Poras T. Balsara, Robert B. Staszewski

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CHAPTER 7

IMPLEMENTATION AND EXPERIMENTAL RESULTS

In this chapter, implementation of a frequency synthesizer is described together with a full top-level BLUETOOTH transmitter core. First, a top-level block diagram is presented and all major constituent blocks are listed. Subsequently, chip micrographs and an IC chip evaluation board are described. Next, the characterization data obtained from an ADPLL-based BLUETOOTH transmitter are presented. The key performance measures for an unmodulated synthesizer are its phase noise and spurious tone output. The synthesizer, without the frequency modulation capability, could also be used as a local oscillator (LO) to perform frequency translation in a receiver path.

7.1 DSP AND ITS RF INTERFACE TO DRP

An overview of the IC chip is presented in Fig. 7.1. A frequency synthesizer is combined with a DSP to implement the complete transmitter. The DSP, Texas Instruments TMS320C54x equipped with 28 kilowords of RAM and 128 kilowords of ROM, contains typical peripherals used for cellular applications: timer, API, serial port, and XIO parallel bus interface, including interrupts and wait states. The XIO bus is a dedicated high-speed bidirectional parallel interface of 8-bit address space and 16-bit data registers that couple the digital RF transmitter (DRP) directly to the DSP. The transmitter registers are mapped into the DSP XIO space and can be accessed using read and write instructions. The DRP is the sole provider of the DSP clock. To avoid ...

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