You are previewing All-Digital Frequency Synthesizer in Deep-Submicron CMOS.
O'Reilly logo
All-Digital Frequency Synthesizer in Deep-Submicron CMOS

Book Description

A new and innovative paradigm for RF frequency synthesis and wireless transmitter design

Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die using standard ASIC design flow.

Taking a bottom-up approach that progressively builds skills and knowledge, the book begins with an introduction to basic concepts of frequency synthesis and then guides the reader through an all-digital RF frequency synthesizer design:

  • Chapter 2 presents a digitally controlled oscillator (DCO), which is the foundation of a novel architecture, and introduces a time-domain model used for analysis and VHDL simulation

  • Chapter 3 adds a hierarchical layer of arithmetic abstraction to the DCO that makes it easier to operate algorithmically

  • Chapter 4 builds a phase correction mechanism around the DCO such that the system's frequency drift or wander performance matches that of the stable external frequency reference

  • Chapter 5 presents an application of the all-digital RF synthesizer

  • Chapter 6 describes the behavioral modeling and simulation methodology used in design

  • The final chapter presents the implementation of a full transmitter and experimental results. The novel ideas presented here have been implemented and proven in two high-volume, commercial single-chip radios developed at Texas Instruments: Bluetooth and GSM.

While the focus of the book is on RF frequency synthesizer design, the techniques can be applied to the design of other digitally assisted analog circuits as well. This book is a must-read for students and engineers who want to learn a new paradigm for RF frequency synthesis and wireless transmitter design using digitally intensive design techniques.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. DEDICATION
  5. CONTENTS
  6. PREFACE
  7. CHAPTER 1: INTRODUCTION
    1. 1.1 FREQUENCY SYNTHESIS
    2. 1.2 FREQUENCY SYNTHESIZER AS AN INTEGRAL PART OF AN RF TRANSCEIVER
    3. 1.3 FREQUENCY SYNTHESIZERS FOR MOBILE COMMUNICATIONS
    4. 1.4 IMPLEMENTATION OF AN RF SYNTHESIZER
  8. CHAPTER 2: DIGITALLY CONTROLLED OSCILLATOR
    1. 2.1 VARACTOR IN A DEEP-SUBMICRON CMOS PROCESS
    2. 2.2 FULLY DIGITAL CONTROL OF OSCILLATING FREQUENCY
    3. 2.3 LC TANK
    4. 2.4 OSCILLATOR CORE
    5. 2.5 OPEN-LOOP NARROWBAND DIGITAL-TO-FREQUENCY CONVERSION
    6. 2.6 EXAMPLE IMPLEMENTATION
    7. 2.7 TIME-DOMAIN MATHEMATICAL MODEL OF A DCO
    8. 2.8 SUMMARY
  9. CHAPTER 3: NORMALIZED DCO
    1. 3.1 OSCILLATOR TRANSFER FUNCTION AND GAIN
    2. 3.2 DCO GAIN ESTIMATION
    3. 3.3 DCO GAIN NORMALIZATION
    4. 3.4 PRINCIPLE OF SYNCHRONOUSLY OPTIMAL DCO TUNING WORD RETIMING
    5. 3.5 TIME DITHERING OF DCO TUNING INPUT
    6. 3.6 IMPLEMENTATION OF PVT AND ACQUISITION DCO BITS
    7. 3.7 IMPLEMENTATION OF TRACKING DCO BITS
    8. 3.8 TIME-DOMAIN MODEL
    9. 3.9 SUMMARY
  10. CHAPTER 4: ALL-DIGITAL PHASE-LOCKED LOOP
    1. 4.1 PHASE-DOMAIN OPERATION
    2. 4.2 REFERENCE CLOCK RETIMING
    3. 4.3 PHASE DETECTION
    4. 4.4 MODULO ARITHMETIC OF THE REFERENCE AND VARIABLE PHASES
    5. 4.5 TIME-TO-DIGITAL CONVERTER
    6. 4.6 FRACTIONAL ERROR ESTIMATOR
    7. 4.7 FREQUENCY REFERENCE RETIMING BY A DCO CLOCK
    8. 4.8 LOOP GAIN FACTOR
    9. 4.9 PHASE-DOMAIN ADPLL ARCHITECTURE
    10. 4.10 PLL FREQUENCY RESPONSE
    11. 4.11 NOISE AND ERROR SOURCES
    12. 4.12 TYPE II ADPLL
    13. 4.13 HIGHER-ORDER ADPLL
    14. 4.14 NONLINEAR DIFFERENTIAL TERM OF AN ADPLL
    15. 4.15 DCO GAIN ESTIMATION USING A PLL
    16. 4.16 GEAR SHIFTING OF PLL GAIN
    17. 4.17 EDGE SKIPPING DITHERING SCHEME (OPTIONAL)
    18. 4.18 SUMMARY
  11. CHAPTER 5: APPLICATION: ADPLL-BASED TRANSMITTER
    1. 5.1 DIRECT FREQUENCY MODULATION OF A DCO
    2. 5.2 JUST-IN-TIME DCO GAIN CALCULATION
    3. 5.3 GFSK PULSE SHAPING OF TRANSMITTER DATA
    4. 5.4 POWER AMPLIFIER
    5. 5.5 DIGITAL AMPLITUDE MODULATION
    6. 5.6 GOING FORWARD: POLAR TRANSMITTER
    7. 5.7 SUMMARY
  12. CHAPTER 6: BEHAVIORAL MODELING AND SIMULATION
    1. 6.1 SIMULATION METHODOLOGY
    2. 6.2 DIGITAL BLOCKS
    3. 6.3 SUPPORT OF DIGITAL STREAM PROCESSING
    4. 6.4 RANDOM NUMBER GENERATOR
    5. 6.5 TIME-DOMAIN MODELING OF DCO PHASE NOISE
    6. 6.6 MODELING METASTABILITY IN FLIP-FLOPS
    7. 6.7 SIMULATION RESULTS
    8. 6.8 SUMMARY
  13. CHAPTER 7: IMPLEMENTATION AND EXPERIMENTAL RESULTS
    1. 7.1 DSP AND ITS RF INTERFACE TO DRP
    2. 7.2 TRANSMITTER CORE IMPLEMENTATION
    3. 7.3 IC CHIP
    4. 7.4 EVALUATION BOARD
    5. 7.5 MEASUREMENT EQUIPMENT
    6. 7.6 GFSK TRANSMITTER PERFORMANCE
    7. 7.7 SYNTHESIZER PERFORMANCE
    8. 7.8 SYNTHESIZER SWITCHING TRANSIENTS
    9. 7.9 DSP-DRIVEN MODULATION
    10. 7.10 PERFORMANCE SUMMARY
    11. 7.11 SUMMARY
  14. APPENDIX A: SPURS DUE TO DCO SWITCHING
    1. A.1 SPURS DUE TO DCO MODULATION
  15. APPENDIX B: GAUSSIAN PULSE-SHAPING FILTER
  16. APPENDIX C: VHDL SOURCE CODE
    1. C.1 DCO LEVEL 2
    2. C.2 PERIOD-CONTROLLED OSCILLATOR
    3. C.3 TACTICAL FLIP-FLOP
    4. C.4 TDC PSEUDO-THERMOMETER OUTPUT DECODER
  17. REFERENCES
  18. INDEX