Algorithms and Parallel Computing

14.2 DECIMATOR STRUCTURES

A decimator is a device that passes a high-rate input signal through a low-pass filter then picks out some of the filter outputs to get a low-rate output. The low-pass filter is sometimes referred to as an anti-aliasing filter. Decimation is usually used for signals whose Nyquist rate is much higher than the highest frequency of the signal. In this way, computations and memory savings can result by reducing the data rate without loss of information.

The model of an M-to-1 decimator is shown in Fig. 14.1 [94, 95]. The operating frequencies of the different components are indicated above the input and output lines. The sample periods are indicated below the input and output lines. The block on the left is an N-tap finite impulse response (FIR) digital filter with impulse response h(nT), where T is the high-rate sampling period, which operates at the high sampling rate F. M − 1 out of every M output samples are discarded by the M-to-1 sampling rate compressor, or downsampler, shown as the block on the right in Fig. 14.1. The low-pass filter generates the signal u(nT) and the downsampler generates the signal y(nT′). The system in Fig. 14.1 implies a serial algorithm where input data samples are first filtered then downsampled. The techniques we discuss here merge the two operations and extract different parallelization options.

Figure 14.1 General M-to-1 decimator system.

We can write the following equations for the two output signals

(14.1)

(14.2) ...