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Advanced Backend Optimization by Sid Touati, Benoit de Dinechin

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Appendix 3

Efficiency of SIRA on the Benchmarks

A3.1. Efficiency of SIRALINA on stand-alone DDG

This section summarizes our full experiments in [BRI 09b]. SIRALINA can be used to optimize all register types conjointly, as explained in section 9.4, or to optimize each register type separately. When register types are optimized separately, the order in which they are processed is of importance, since optimizing a register type may influence the register requirement of another type (because the statements are connected by data dependences). This section studies the impact of SIRALINA on register optimization with multiple register types (separate or conjoint) in the context of three representative architectures (small, medium and large, see section A1.3).

The computers used for the stand-alone experiments were Intel-based PCs. The typical configuration was Core 2 Duo PC at 1.6 GHz, running GNU/Linux 64 bits (kernel 2.6), with 4 GB of main memory.

A3.1.1. Naming conventions for register optimization orders

In this appendix, we experiment with many configurations for register optimization. Typically, the order of register types used for optimization is a topic of interest. For images = {t1, …, tn} a set of register types, and images a permutation; we note = tp(1); tp(2); …; tp(n) the register-type ...

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