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ABCs of z/OS System Programming Volume 10

Book Description

The ABCs of z/OS System Programming is an 13-volume collection that provides an introduction to the z/OS operating system and the hardware architecture. Whether you are a beginner or an experienced system programmer, the ABCs collection provides the information that you need to start your research into z/OS and related subjects. If you would like to become more familiar with z/OS in your current environment, or if you are evaluating platforms to consolidate your e-business applications, the ABCs collection will serve as a powerful technical tool.
The contents of the volumes are as follows:
Volume 1: Introduction to z/OS and storage concepts, TSO/E, ISPF, JCL, SDSF, and z/OS delivery and installation
Volume 2: z/OS implementation and daily maintenance, defining subsystems, JES2 and JES3, LPA, LNKLST, authorized libraries, SMP/E, Language Environment
Volume 3: Introduction to DFSMS, data set basics storage management hardware and software, catalogs, and DFSMStvs
Volume 4: Communication Server, TCP/IP, and VTAM
Volume 5: Base and Parallel Sysplex, System Logger, Resource Recovery Services (RRS), global resource serialization (GRS), z/OS system operations, automatic restart management (ARM), Geographically Dispersed Parallel Sysplex (GDPS)
Volume 6: Introduction to security, RACF, Digital certificates and PKI, Kerberos, cryptography and z990 integrated cryptography, zSeries firewall technologies, LDAP, and Enterprise identity mapping (EIM)
Volume 7: Printing in a z/OS environment, Infoprint Server and Infoprint Central
Volume 8: An introduction to z/OS problem diagnosis
Volume 9: z/OS UNIX System Services
Volume 10: Introduction to z/Architecture, zSeries processor design, zSeries connectivity, LPAR concepts, HCD, and HMC
Volume 11: Capacity planning, performance management, RMF, and SMF
Volume 12: WLM
Volume 13: JES3

Table of Contents

  1. Front cover
  2. Notices
    1. Trademarks
  3. Preface
    1. The team who wrote this book
  4. Chapter 1. Introduction to z/Architecture
    1. 1.1 Computer architecture overview
    2. 1.2 Concept of a process
    3. 1.3 Process states and attributes
    4. 1.4 System components
    5. 1.5 Processing units (PUs)
    6. 1.6 z/Architecture enhancements
    7. 1.7 64-bit address space map
    8. 1.8 Addressing mode
    9. 1.9 64-bit dynamic address translation
    10. 1.10 CP registers (general)
    11. 1.11 Floating point registers
    12. 1.12 Current program-status word (PSW)
    13. 1.13 Next sequential instruction address
    14. 1.14 Program-status-word format
    15. 1.15 Prefixed save area (PSA)
    16. 1.16 Several instruction formats
    17. 1.17 Microcode concepts
    18. 1.18 z/Architecture components
    19. 1.19 z/Architecture data formats
    20. 1.20 Interrupts
    21. 1.21 Interrupt processing
    22. 1.22 Types of interrupts
    23. 1.23 Supervisor call interrupt
    24. 1.24 Storage protection
    25. 1.25 Storage protection logic
    26. 1.26 Addresses and address spaces
    27. 1.27 z/Architecture address sizes
    28. 1.28 Storage addressing
    29. 1.29 Real storage locations
    30. 1.30 Dynamic address translation (DAT)
    31. 1.31 Dynamic address translation
    32. 1.32 Page faults
    33. 1.33 Dual address space (cross memory)
    34. 1.34 Access register mode (dataspaces)
    35. 1.35 CPU signaling facility
    36. 1.36 Time measurement TOD
    37. 1.37 Time measurement (CP timer)
    38. 1.38 Sysplex Timer expanded availability configuration
    39. 1.39 Server Time Protocol (STP)
    40. 1.40 Data center and I/O configuration
    41. 1.41 Channel subsystem (CSS) elements
    42. 1.42 Multiple CSS structure (z10 and z196 EC)
    43. 1.43 Control units
    44. 1.44 Device number
    45. 1.45 Subchannel number
    46. 1.46 Subchannel numbering
    47. 1.47 Control unit address
    48. 1.48 Unit addresses
    49. 1.49 Map device number to device address
    50. 1.50 Multiple channel paths to a device
    51. 1.51 Start subchannel (SSCH) logic
    52. 1.52 SAP PU logic
    53. 1.53 Channel processing
    54. 1.54 I/O interrupt processing
    55. 1.55 I/O summary
  5. Chapter 2. Introducing the IBM z10
    1. 2.1 z196 and z10 overview
    2. 2.2 IBM System z nomenclature
    3. 2.3 z10 EC naming summary
    4. 2.4 The power of GHz (high frequency)
    5. 2.5 Processor unit (PU) instances
    6. 2.6 z10 EC hardware model
    7. 2.7 z10 EC sub-capacity models
    8. 2.8 z10 EC frames and cages
    9. 2.9 Book topology comparison
    10. 2.10 NUMA topology
    11. 2.11 z10 EC Books
    12. 2.12 Multi-chip module (MCM)
    13. 2.13 PU chip
    14. 2.14 Book element interconnections
    15. 2.15 Pipeline in z10 EC
    16. 2.16 Pipeline branch prediction
    17. 2.17 About each z10 EC PU
    18. 2.18 z10 EC storage controller (SC) chip
    19. 2.19 Recapping the z10 EC design
    20. 2.20 Three levels of cache
    21. 2.21 Software/hardware cache optimization
    22. 2.22 HiperDispatch considerations
    23. 2.23 Central storage design
    24. 2.24 Addresses and addresses
    25. 2.25 Hardware system area (HSA)
    26. 2.26 Large page (1 M) support
    27. 2.27 Connecting PU cage with I/O cages
    28. 2.28 Detailed connectivity
    29. 2.29 HCA and I/O card connections
    30. 2.30 InfiniBand interconnect technology
    31. 2.31 I/O cage
    32. 2.32 The I/O data flow
    33. 2.33 Redundant I/O Interconnect
    34. 2.34 z10 EC I/O features supported
    35. 2.35 16-port ESCON channel card
    36. 2.36 FICON features and extended distance
    37. 2.37 Features in z10 and z196
    38. 2.38 z10 EC new features
  6. Chapter 3. Introducing the IBM zEnterprise
    1. 3.1 zEnterprise overview
    2. 3.2 Migrating Unix/Linux workloads back to the mainframe
    3. 3.3 z196 numeric comparison
    4. 3.4 Processor Units (PU) instances
    5. 3.5 z196 models
    6. 3.6 Sub capacity models
    7. 3.7 Model capacity identifier and MSU/h
    8. 3.8 z196 frames, cages and I/O drawers (I)
    9. 3.9 z196 frames, cages and I/O drawers (II)
    10. 3.10 NUMA topology
    11. 3.11 z196 books
    12. 3.12 Any to any book connectivity
    13. 3.13 Fanout cards in a book
    14. 3.14 Multichip module (MCM)
    15. 3.15 Frequency (GHz) in a z196 PU
    16. 3.16 Quad core PU chip
    17. 3.17 PU chip coprocessor
    18. 3.18 Storage controller (SC) chip in MCM
    19. 3.19 z196 book recapping
    20. 3.20 Pipeline concept within a PU
    21. 3.21 Out of order execution
    22. 3.22 z196 instructions
    23. 3.23 Non-quiesce SSKE instruction
    24. 3.24 z10 EC and z196 cache design comparison
    25. 3.25 Storage layers
    26. 3.26 z196 cache design (I)
    27. 3.27 z196 cache design (II)
    28. 3.28 HiperDispatch concepts
    29. 3.29 The clerk dilemma
    30. 3.30 z/OS dispatcher logic in HiperDispatch
    31. 3.31 Central Storage design
    32. 3.32 MCUs and DIMMs in a z196 book
    33. 3.33 Purchase memory offerings
    34. 3.34 Addresses and addresses
    35. 3.35 Hardware system area (HSA)
    36. 3.36 Large pages
    37. 3.37 An I/O data flow tree analogy
    38. 3.38 Book to channel connectivity
    39. 3.39 Connecting books with I/O channels
    40. 3.40 FICON I/O card
    41. 3.41 FICON channel topics in z196
    42. 3.42 I/O cage
    43. 3.43 I/O drawer
    44. 3.44 Redundant I/O interconnect
    45. 3.45 Coupling Facility links
    46. 3.46 Infiniband protocol
    47. 3.47 z196 maximum number of channel per type
    48. 3.48 z/OS discovery and auto-configuration (zDAC)
    49. 3.49 WWPN and fabrics discovery
    50. 3.50 zDAC software and hardware requirements
    51. 3.51 zDAC policy in HCD
    52. 3.52 zDAC policy
    53. 3.53 zDAC discovered HCD panel
    54. 3.54 zDAC proposed HCD panel
    55. 3.55 Logical channel subsystem
    56. 3.56 LP ID, MIF ID, and spanning concepts
    57. 3.57 Physical channel ID (PCHID)
    58. 3.58 Association between CHPID and PCHID
    59. 3.59 Comparison between System z servers
    60. 3.60 IOCP statements example
    61. 3.61 Configuration definition process
    62. 3.62 Channel availability features
    63. 3.63 Introduction to MIDAW
    64. 3.64 Channel command word (CCW) concept
    65. 3.65 CCWs and virtual storage - IDAW Concept
    66. 3.66 DASD extended format
    67. 3.67 Using MIDAWs
    68. 3.68 Reducing CCWs using MIDAW
    69. 3.69 MIDAW performance results
    70. 3.70 Cryptography concepts
    71. 3.71 Cryptography in z196
    72. 3.72 z196 crypto synchronous functions
    73. 3.73 Crypto express-3
    74. 3.74 z196 crypto asynchronous functions
    75. 3.75 Protected keys in CPACF
    76. 3.76 PR/SM and cryptography
    77. 3.77 Just-in-time concurrent upgrades
    78. 3.78 On/Off capacity on demand (CoD)
    79. 3.79 Other capacity upgrade plans
    80. 3.80 Capacity provisioning
    81. 3.81 Capacity provisioning domain
    82. 3.82 SNMP interface to HMC
  7. Chapter 4. zEnterprise BladeCenter Extension Model 002 (zBX)
    1. 4.0.1 zEnterprise
    2. 4.1 zBX hardware rack components
    3. 4.2 BladeCenter chassis
    4. 4.3 Blades by function
    5. 4.4 The blade types
    6. 4.5 Blades data warehouse roles
    7. 4.6 POWER7 blades
    8. 4.7 WebSphere datapower appliance blades
    9. 4.8 Nodes and ensembles
    10. 4.9 zBX networking and connectivity
    11. 4.10 Hardware management consoles (HMC)
  8. Chapter 5. z/Enterprise Unified Resource Manager
    1. 5.1 Unified resource manager introduction
    2. 5.2 Refreshing the ensemble concept
    3. 5.3 zManager location in zEnterprise
    4. 5.4 zManager major roles
    5. 5.5 zManager hypervisors and energy
    6. 5.6 Energy SAD frame
    7. 5.7 More details about energy management
    8. 5.8 Energy data available from HMC
    9. 5.9 Systems director active energy manager
    10. 5.10 zManager operations control
    11. 5.11 Change management functions
    12. 5.12 Problem management
    13. 5.13 Configuration management
    14. 5.14 zManager HMC configuration panel
    15. 5.15 Operations management
    16. 5.16 Performance monitoring and business management
    17. 5.17 Ensemble management
    18. 5.18 zManager performance, virtual life cycle and networks
    19. 5.19 Network management
    20. 5.20 zEnterprise platform performance manager
    21. 5.21 PPM virtual servers
    22. 5.22 Virtual server definition
    23. 5.23 z/OS WLM main terms
    24. 5.24 Intelligent resource director review
    25. 5.25 RD for a zLinux logical partition
    26. 5.26 RMF and IRD zLinux implementation
    27. 5.27 PPM wizard welcome panel
    28. 5.28 PPM components
    29. 5.29 Differences between PPM and z/OS WLM
    30. 5.30 PPM agents
    31. 5.31 Application response measurement (ARM)
    32. 5.32 Virtual server processor management (I)
    33. 5.33 Virtual server CPU management (II)
    34. 5.34 PPM major constructs
    35. 5.35 PPM workload concepts
    36. 5.36 PPM workload definition
    37. 5.37 PPM policy
    38. 5.38 Service class concepts
    39. 5.39 Service class definition
    40. 5.40 Classification rules
    41. 5.41 z/OS WLM agent
    42. 5.42 Connecting PPM SC with a WLM service class
    43. 5.43 z/VM agent role in PPM
    44. 5.44 PowerVM agent role in PPM
    45. 5.45 PPM performance data reporting
  9. Chapter 6. System z connectivity
    1. 6.1 Connectivity overview
    2. 6.2 Multiple Image Facility channels
    3. 6.3 Channel subsystem connectivity
    4. 6.4 CSS configuration management
    5. 6.5 Displaying channel types
    6. 6.6 ESCON architecture
    7. 6.7 ESCON concepts
    8. 6.8 ESCD (switch) functions
    9. 6.9 ESCON Director (ESCD) description
    10. 6.10 ESCON Director matrix
    11. 6.11 Channel-to-channel adapter
    12. 6.12 ESCON CTC support
    13. 6.13 FICON channels
    14. 6.14 FICON conversion mode
    15. 6.15 Supported FICON native topologies
    16. 6.16 Fibre Channel Protocol (FCP)
    17. 6.17 FICON improvements (1)
    18. 6.18 FICON improvements (2)
    19. 6.19 FICON/ESCON numerical comparison
    20. 6.20 FICON switches
    21. 6.21 Cascaded FICON Directors
    22. 6.22 FICON Channel to Channel Adapter (FCTC)
    23. 6.23 z9 Coupling Facility links
    24. 6.24 z10 EC Coupling Facility connectivity options
    25. 6.25 All z10 EC coupling link options
    26. 6.26 OSA-Express
    27. 6.27 QDIO architecture
    28. 6.28 HiperSockets connectivity
    29. 6.29 Hardware Configuration Definition (HCD)
  10. Chapter 7. Virtualization and Logical Partition (LPAR) concepts
    1. 7.1 Virtualization definitions
    2. 7.2 Virtualization concepts
    3. 7.3 Virtualized physical resources
    4. 7.4 Hypervisor types
    5. 7.5 Hypervisor technologies (I)
    6. 7.6 Hypervisor technologies (II)
    7. 7.7 IBM hypervisors
    8. 7.8 z/Virtual Machine (z/VM)
    9. 7.9 z/VM options in HMC
    10. 7.10 Virtualization in zBX blades
    11. 7.11 PowerVM virtual servers
    12. 7.12 Comparing hypervisor terminology
    13. 7.13 History of operating environments
    14. 7.14 CPC in basic mode
    15. 7.15 CPC in LPAR mode
    16. 7.16 Shared and dedicated logical CPs example
    17. 7.17 LPAR dispatching and shared CPs
    18. 7.18 Reasons for intercepts
    19. 7.19 LPAR event-driven dispatching
    20. 7.20 LPAR time slice interval
    21. 7.21 LPAR weights
    22. 7.22 z196 PU pools
    23. 7.23 Capping workloads
    24. 7.24 Types of capping
    25. 7.25 LPAR capping
    26. 7.26 LPAR capped versus uncapped
    27. 7.27 Soft capping
    28. 7.28 Group capacity in soft capping
    29. 7.29 Intelligent resource director (IRD)
    30. 7.30 WLM LPAR CPU management
    31. 7.31 Intelligent Resource Director benefits
    32. 7.32 WLM concepts
    33. 7.33 Dynamic Channel Path Management (DCM)
    34. 7.34 Channel subsystem I/O priority queueing
  11. Chapter 8. Hardware Configuration Definition (HCD)
    1. 8.1 What is HCD
    2. 8.2 IOCP example
    3. 8.3 IOCP elements
    4. 8.4 Hardware and software configuration
    5. 8.5 HCD functions
    6. 8.6 Dynamic I/O reconfiguration
    7. 8.7 Dynamic I/O reconfiguration device types
    8. 8.8 IODF data set
    9. 8.9 Definition order
    10. 8.10 HCD primary menu
    11. 8.11 Creating a new work IODF
    12. 8.12 Defining configuration data
    13. 8.13 Operating system definition
    14. 8.14 Defining an operating system
    15. 8.15 EDT and esoterics
    16. 8.16 How to define an EDT (1)
    17. 8.17 How to define an EDT (2)
    18. 8.18 Defining an EDT identifier
    19. 8.19 How to add an esoteric
    20. 8.20 Adding an esoteric
    21. 8.21 Defining switches
    22. 8.22 Adding switches
    23. 8.23 Defining servers
    24. 8.24 Information for defining a server
    25. 8.25 Defining a server
    26. 8.26 Working with LCSSs
    27. 8.27 Logical channel subsystems defined
    28. 8.28 Adding a logical partition (LP)
    29. 8.29 z9 EC LPAR server configuration
    30. 8.30 Channel operation mode
    31. 8.31 Channel types
    32. 8.32 Information required to add channels
    33. 8.33 Working with channel paths
    34. 8.34 Adding channel paths dynamically
    35. 8.35 Adding a channel path
    36. 8.36 Defining an access and a candidate list
    37. 8.37 Adding a control unit
    38. 8.38 Information required to define a control unit
    39. 8.39 Adding a control unit
    40. 8.40 Defining a 2105 control unit
    41. 8.41 Selecting a processor/control unit
    42. 8.42 Servers and channels for connecting control units
    43. 8.43 Defining server attachment data
    44. 8.44 Information required to define a device
    45. 8.45 z/OS device numbering
    46. 8.46 Defining a device
    47. 8.47 Defining device CSS features (1)
    48. 8.48 Defining device CSS features (II)
    49. 8.49 Defining devices to the operating system
    50. 8.50 Defining operating system device parameters
    51. 8.51 Assigning a device to an esoteric
    52. 8.52 Defining an NIP console
    53. 8.53 Using the CHPID mapping tool
    54. 8.54 Build a production IODF
    55. 8.55 Define the descriptor fields
    56. 8.56 Production IODF created
    57. 8.57 Activating a configuration with HCD
    58. 8.58 View an active IODF with HCD
    59. 8.59 Viewing an active IODF
    60. 8.60 Displaying device status
    61. 8.61 HCD reports
    62. 8.62 Hardware Configuration Manager (HCM)
  12. Chapter 9. DS8000 series concepts
    1. 9.1 DASD controller capabilities
    2. 9.2 DS8000 characteristics
    3. 9.3 DS8000 design
    4. 9.4 Internal fabric and I/O enclosures
    5. 9.5 Disk subsystem
    6. 9.6 Switched Fibre Channel Arbitrated Loop (FC-AL)
    7. 9.7 Redundant array of independent disks (RAID)
    8. 9.8 DS8000 types of RAID
    9. 9.9 Logical subsystem (LSS)
    10. 9.10 Logical partition (LPAR)
    11. 9.11 Copy services classification criteria
    12. 9.12 Consistency group concept
    13. 9.13 Copy services in DS8000
    14. 9.14 FlashCopy
    15. 9.15 Consistency group in FlashCopy
    16. 9.16 Remote Mirror and Copy (example: PPRC)
    17. 9.17 Consistency groups in Metro Mirror
    18. 9.18 Global Copy (example: PPRC XD)
    19. 9.19 Global Mirror (example: async PPRC)
    20. 9.20 z/OS Global Mirror (example: XRC)
    21. 9.21 Parallel access volume (PAV)
    22. 9.22 HyperPAV feature for DS8000 series
    23. 9.23 HyperPAV and IOS
    24. 9.24 HyperPAV implementation
    25. 9.25 Display M=DEV command
    26. 9.26 RMF DASD report
    27. 9.27 RMF I/O Queueing report
    28. 9.28 DS8000 Capacity on Demand
    29. 9.29 DS command line interface (CLI)
    30. 9.30 Storage Hardware Management Console (S-HMC)
  13. Related publications
    1. IBM Redbooks
    2. Other publications
    3. Online resources
    4. How to get IBM Redbooks
  14. Back cover