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Gbps OFDM Baseband Design and Implementation for 60 GHz Wireless LAN Applications
For high data-rate wireless transmission over non-line-of-sight (NLOS) 60 GHz channels, the orthogonal frequency division multiplexing (OFDM) scheme has been preferred to single carrier (SC) schemes due to its stronger immunity to highly frequency-selective fading [1].1 This would make baseband receiver implementation easier since costly equalizers required in SC schemes can be significantly simplified. However, an OFDM is more sensitive to synchronization errors compared to a SC scheme. As an additional challenge, 60 GHz phase-locked loops (PLLs) exhibit worse frequency instability and phase noise characteristics than microwave-band ones. Therefore, it is necessary to design synchronization architecture more carefully in a 60 GHz OFDM baseband receiver.
This chapter describes design consideration and implementation issues for the 60 GHz OFDM baseband processor which we developed for the WIGWAM [2] and EASY-A projects [3]. An FPGA platform has been utilized for baseband implementation since it allows simpler modification as well as higher flexibility/scalability in system-level hardware. Moreover, it promises simple transitions to structured application-specific integrated circuit (ASIC) chips.
However, an FPGA implementation for multi-gigabit data rate is not a straightforward task due to limited clock speed. The most critical blocks are ...
