When a design has timing loops, it is advisable that it be broken by a sequential element. This ensures that the timing loop, which may cause timing glitches, is broken into two timing paths: presequential and postsequential element path.
- CHAPTER FOUR: Coding Style: Best-Known Method for Synthesis
- from Verilog Coding for Logic Synthesis
- Publisher: Wiley-Interscience
- Released: April 2003
flip-flop을 써서 나눠야 한다.
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