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  • Hyunho Jo thinks this is interesting:

When a design has timing loops, it is advisable that it be broken by a sequential element. This ensures that the timing loop, which may cause timing glitches, is broken into two timing paths: presequential and postsequential element path.

From

Cover of Verilog Coding for Logic Synthesis

Note

flip-flop을 써서 나눠야 한다.